Design and Test of 3D-MAPS, a 3D Die-Stack Many-Core Processor
نویسندگان
چکیده
3D-MAPS is a test vehicle for evaluating the architectural implications of microprocessors designed using 3D integration technology. The 3D-MAPS processor is a five-layer stack consisting of logic, cache, and DRAM layers. Testing such a 3D design presents several unique challenges. Our test architecture is a custom design, borrowing from the IEEE 1149.1 and 1500 standards. The design goals were to minimize pin count, maximize graceful degradation, and ensure complete diagnostic capability of the chip.
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